1. Field of the Invention
The present invention relates to an image display device, and more particularly, to an apparatus and method for transmitting data of an image display device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for minimizing the number of data transitions simultaneously while reducing power consumption.
2. Discussion of the Related Art
The amount of video data transmitted via a transmission medium has rapidly increased to satisfy the demand of users who desire to view high-quality video data. The high-quality video data is transmitted to users at high speed, such that the users can use the high-quality video data. Therefore, transmission frequency of video data has gradually increased, and the number of transmission lines capable of transmitting the video data has also increased. If video data having a high frequency is transmitted over data transmission lines in which the transmissions become synchronized, Electromagnetic Interference (EMI) can occur. To reduce the occurrence of the EMI, an image display device typically either uses a first method of reducing the number of data transitions according to a data modulation scheme, or a second method of reducing transmission frequency using six-bit data into two ports.
FIG. 1 is a circuit diagram illustrating a related art image display device for transmitting video data using six-bit data into two ports. As shown in FIG. 1, the image display device includes an image display part 10 for displaying a desired image, a data driver 20 for driving data lines (DL1˜DLm) of the image display part 10, a gate driver 30 for driving gate lines (GL1˜GLn) of the image display part 10, and a timing controller 40 for controlling the data driver 20 and the gate driver 30. The image display part 10, includes a pixel matrix composed of sub-pixels formed between the gate lines and the data lines.
A single pixel is implemented by a combination of red, green and blue sub-pixels. Each sub-pixel includes a pixel cell 12 for displaying a desired image according to a data signal applied to the data line, such that it establishes synchronization with a scan pulse applied to a corresponding gate line. The pixel cell 12 may be a liquid crystal cell for adjusting an optical transmission rate according to the data signal to display a desired image, or a light emitting cell for performing light emission according to a current signal corresponding to the data signal to display a desired image.
The gate driver 30 includes a plurality of gate driver integrated circuits (ICs) for independently driving the gate lines (GL1˜GLn) of the image display device 10. Individual gate driver ICs sequentially transmit scan pulses to the gate lines (GL1˜GLn), such that the gate lines (GL1˜GLn) are sequentially driven. The data driver 20 includes a plurality of data driver ICs for independently driving data lines (DL1˜DLm) of the image display device 10. Each data driver IC converts a digital data signal (Data) received from the timing controller 40 into an analog data signal, such that the analog data signal is applied to individual data lines (DL1˜DLm) whenever receiving the scan pulse.
The timing controller 40 generates a gate control signal (GCS) capable of controlling the gate driver 30, and transmits the gate control signal (GCS) to the gate driver 30. The timing controller 40 generates a data control signal (DCS) capable of controlling the data driver 20, and transmits the data control signal (DCS) to the data driver 20. In this case, the timing controller 40 receives a data enable signal (DE) indicative of a valid data interval, a horizontal synchronous signal (Hsync), a vertical synchronous signal (Vsync), a dot clock (DCLK) for determining a transmission frequency of video data (RGB) from a drive system (not shown), and generates gate control signals (GCS) and data control signals (DCS) using the received signals.
The timing controller 40 arranges a source data signal (RGB) received from the drive system (not shown) according to a two-port transmission scheme, and transmits the arranged source data signal to the data driver 20. For example, the timing controller 40 divides the source data signal (RGB) into an odd data signal (OData) and an even data signal (EData), and transmits the odd data signal (OData) and the even data signal (EData) to the data driver 20 via two ports, respectively.
Provided that each source data (RGB) is composed of 6-bit data to represent 63 gray levels, the above-mentioned two ports for transmitting the odd data signal (Odata) and the even data signal (Edata) in parallel to each other include a total of 36 data transmission lines (i.e., RO0˜RO5, RE0˜RE5, GO1˜G05, GE0˜GE5, BO1˜BO5, and BE0˜BE5). In this way, the timing controller 40 uses the two-port transmission scheme to reduce a transmission frequency of a data signal, resulting in a reduction of EMI.
FIG. 2 is a circuit diagram illustrating a related art data transmitter. As shown in FIG. 2, according to the above-mentioned data transmission method via two ports, the timing controller 40 (1) compares a current data signal with the next data signal to detect the number of data transitions, (2) forms a data inversion signal (REV) according to the detected number of transitions, (3) arranges a data signal to be synchronized with the data inversion signal (REV), (4) transmits the arranged data signal to the data driver 20 and the data driver 20 (5) re-arranges the data signal received from the timing controller 40 such that the re-arranged data signal is synchronized with the data inversion signal (REV) received from the timing controller 40, (6) the data inversion signal (REV) is also transmitted to the data driver 20, and (7) the data driver 20 uses the received REV signal to determine whether the received data was inverted of the timing controller 40 or whether the transmitted data signal was transmitted by the timing controller 40.
FIG. 3 is a waveform diagram illustrating drive waveforms of the data transmitter shown in FIG. 2. As shown in FIG. 3, if the timing controller 40 transmits a white signal to the data driver 20, the TC 40 (1) receives an transmitted data signal having the value of “1”, and (2) forms a data signal having the value of zero synchronized with the data inversion signal of 1, and transmits the transformed data signal of zero to the data driver 20. In this case, although the transformed data signal of 0 is continuously applied to the data driver 20, the data inversion signal (REV) is maintained at the value of “1”, such that the original data signal is inverted by the timing controller 40, and the received data signal is re-inverted by the data driver 20.
In the meantime, it is well known to those skilled in the art that there is little variation in gray levels due to similarity between adjacent data signals of an image to be displayed on the image display part 10. However, it should be noted that a single gray variation in a binary code corresponding to video data does not always mean transition of 1-bit data. For example, if a first port transmits a signal of “000111” corresponding to grey level 7 as an i-th red data signal, and then transmits a signal of “001000” corresponding to grey level 8 as an (i+2)-th red data signal, it can be recognized that there are relatively many bit transitions (i.e., four-bit transitions) even though only one grey level between the i-th red data signal and the (i+2)-th red data signal is changed.
The above-mentioned data transmission method via two ports forms unnecessary data transition in the timing controller 40 and the data driver 20. In this case, the number of data transitions provided when a 6-bit data signal corresponding to a white signal is transmitted to the image display having XGA resolution using a 2-port transmission method during a predetermined period of time equal to a one horizontal interval is denoted by 6×3×2×256 equal to 9216 times. In this case, 256 is indicative of the number of data signals applied to a single data driver. Therefore, although most data transmission lines of two ports successively transmit adjacent data signals having little gray variation, many data bits transisitions are formed on individual data transmission lines, resulting in increased EMI and power consumption.